w3eg6464s-ad4 -bd4 preliminary* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 512mb - 64mx64 ddr sdram unbuffered w/pll double-data-rate architecture speeds of 100mhz, 133mhz and 166mhz bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect power supply: v cc : 2.5v 0.2v jedec standard 200 pin so-dimm package ? package height options: ad4: 35.5 mm (1.38"), bd4: 31.75 (1.25") the w3eg6464s is a 64mx64 double data rate sdram mem o ry module based on 512mb ddr sdram component. the module consists of eight 64mx8 ddr sdrams in 66 pin tsop packages mounted on a 200 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * this product is under development, is not quali? ed or characterized and is subject to change without notice. description features operating frequencies ddr333@cl=2.5 ddr266@cl=2 ddr266@cl=2.5 ddr200@cl=2 clock speed 166mhz 133mhz 133mhz 100mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2.5-3-3 2-2-2
w3eg6464s-ad4 -bd4 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7 dq1 57 v cc 107a5157v cc 8 dq5 58 v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqs0 61 dqs3 111 a1 161 v ss 12 dm0 62 dm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10/ap 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dm6 21 v cc 71 nc 121 cs0 171 dq50 22 v cc 72 nc 122 nc 172 dq54 23 dq9 73 nc 123 nc 173 v ss 24 dq13 74 nc 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dqs8 127 dq32 177 dq56 28 v ss 78 dm8 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v cc 30 dq14 80 nc 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 nc 133 dqs4 183 dqs7 34 v cc 84 nc 134 dm4 184 dm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 nc 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dm2 98 nc 148 dm5 198 sa2 49 dq18 99 a12 149 v ss 199 v ccid 50 dq22 100 a11 150 v ss 200 nc pin configuration a0-a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs8 data strobe input/output ck0 clock input ck0# clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-dqm8 data-in mask v cc power supply (2.5v) v ccq power supply for dqs (2.5v) v ss ground v ref power supply for reference v ccspd serial eeprom power supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc indenti? cation flag nc no connect pin names
w3eg6464s-ad4 -bd4 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary functional block diagram ck0 c k 0 we#, ras#, cas# w e # , r a s # , c a s # s0# s 0 # cke0 c k e 0 ba0, ba1, a0-a13 b a 0 , b a 1 , a 0 - a 1 3 dq0-7 d q 0 - 7 dq0-7 d q 0 - 7 dq0-7 d q 0 - 7 dq32-39 d q 3 2 - 3 9 ldqm l d q m dqmb0 d q m b 0 u1 u 1 pll p l l u3 u 3 ldqm l d q m dqmb4 d q m b 4 dq0-7 d q 0 - 7 dq8-15 d q 8 - 1 5 dq0-7 d q 0 - 7 dq40-47 d q 4 0 - 4 7 ldqm l d q m dqmb1 d q m b 1 u2 u 2 u4 u 4 ldqm l d q m dqmb5 d q m b 5 dq0-7 d q 0 - 7 dq16-23 d q 1 6 - 2 3 dq0-7 d q 0 - 7 dq48-55 d q 4 8 - 5 5 ldqm l d q m dqmb2 d q m b 2 u5 u 5 u7 u 7 ldqm l d q m dqmb6 d q m b 6 dq0-7 d q 0 - 7 dq24-31 d q 2 4 - 3 1 dq0-7 d q 0 - 7 dq56-63 d q 5 6 - 6 3 ldqm l d q m dqmb3 d q m b 3 u6 u 6 u8 u 8 ldqm l d q m dqmb7 d q m b 7 sa0 s a 0 a0 a 0 scl s c l wp w p sda s d a sa2 s a 2 sa1 s a 1 a2 a 2 a1 a 1 serial s e r i a l pd p d ck0# c k 0 # ddr d d r sdram s d r a m u1 u 1 ddr d d r sdram s d r a m u2 u 2 ddr d d r sdram s d r a m u3 u 3 ddr d d r sdram s d r a m u4 u 4 ddr d d r sdram s d r a m u5 u 5 ddr d d r sdram s d r a m u6 u 6 ddr d d r sdram s d r a m u7 u 7 ddr d d r sdram s d r a m u8 u 8 120 1 2 0 w
w3eg6464s-ad4 -bd4 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 8w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70c, v cc = 2.5v 0.2v capacitance t a = 25c, f = 1mhz, v cc = 3.3v, v ref =1.4v 200mv parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref v ccq/2 - 50mv v ccq/2 + 50mv v termination voltage v tt v ref - 0.04 v ref + 0.04 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il -0.3 v ref - 0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt - 0.76 v parameter symbol max unit input capacitance (a0-a12) c in1 26 pf input capacitance (ras#, cas#, we#) c in2 26 pf input capacitance (cke0) c in3 26 pf input capacitance (ck0,ck0#) c in4 5.5 pf input capacitance (cs0#) c in5 26 pf input capacitance (dqm0-dqm8) c in6 8pf input capacitance (ba0-ba1) c in7 26 pf data input/output capacitance (dq0-dq63)(dqs) c out 8pf
w3eg6464s-ad4 -bd4 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary idd specifications and test conditions recommended operating conditions, 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol conditions ddr333 @cl=2.5 max ddr266 @cl=2 max ddr266 @cl=2.5 max ddr200 @cl=2 max units operating current i dd0 one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. tbd 1595 1595 1595 ma operating current i dd1 one device bank; active-read-precharge; burst = 2; t rc =t rc (min);t ck =t ck (min); iout = 0ma; address and control inputs changing once per clock cycle. tbd 1795 1795 1795 ma precharge power-down standby current i dd2p all device banks idle; power- down mode; t ck =t ck (min); cke=(low) tbd484848ma idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. vin = vref for dq, dqs and dm. tbd 675 675 675 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke=(low) tbd 400 400 400 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. tbd 1035 1035 1035 ma operating current i dd4r burst = 2; reads; continous burst; one device bank active;address and control inputs changing once per clock cycle; t ck =t ck (min); iout = 0ma. tbd 2035 2035 2035 ma operating current i dd4w burst = 2; writes; continous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing twice per clock cycle. tbd 2275 2275 2275 ma auto refresh current i dd5 t rc =t rc (min) tbd 2755 2755 2755 ma self refresh current i dd6 cke 0.2v tbd 315 315 315 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. tbd 4115 4115 4115 ma * for ddr333 consult factory
w3eg6464s-ad4 -bd4 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary i dd1 : operating current : one bank 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck= 10ns, cl2, bl=4, t rcd= 2*t ck , t ras= 5*t ck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck= 7.5ns, cl=2.5, bl=4, t rcd= 3*t ck , t rc= 9*t ck , t ras= 5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl=2, bl=4, t rcd =3*t ck , t rc =9*t ck , t ras =5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rcd =10*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current : four banks 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. iout=0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck =10ns, cl2, bl=4, t rrd =2*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck =7.5ns, cl=2.5, bl=4, t rrd =3*t ck , t rcd =3*t ck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl2=2, bl=4, t rrd =2*t ck , t rcd =2*t ck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rrd =3*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend : a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
w3eg6464s-ad4 -bd4 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary package dimensions for ad4 ordering information for ad4 part number speed height* w3eg6464s335ad4 166mhz/333mbps, cl=2.5 35.5 (1.38)* w3eg6464s262ad4 133mhz/266mbps, cl=2 35.5 (1.38) w3eg6464s265ad4 133mhz/266mbps, cl=2.5 35.5 (1.38) w3eg6464s202ad4 100mhz/200mbps, cl=2 35.5 (1.38) * all dimensions are in milimeters and (inches) 1.0 0.1 (0.039 0.004) 35.05 (1.138) max. 3.81 (0 .150) max. 2.31 (0.091) ref. 2.0 (0.079) 67.56 (2.666) max. 4.19 (0.165) 1.80 (0.071) 3.98 (0.157) min. 20 (0.787) 47.40 (1.866) 11.40 (0.449) p1 3.98 0.1 (0.157 0.004) * for ddr333 consult factory
w3eg6464s-ad4 -bd4 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary package dimensions for bd4 ordering information for bd4 part number speed height* w3eg6464s335bd4 166mhz/333mbps, cl=2.5 31.75 (1.25)* w3eg6464s262bd4 133mhz/266mbps, cl=2 31.75 (1.25) w3eg6464s265bd4 133mhz/266mbps, cl=2.5 31.75 (1.25) w3eg6464s202bd4 100mhz/200mbps, cl=2 31.75 (1.25) * all dimensions are in milimeters and (inches) u7 u5 67.56 (2.666) max u1 u3 u9 r19 r17 r9 r2 r12 c3 c3 rp1 rp5 rp9 rp14 rp18 rp13 rp19 rp4 rp7 rp20 rp22 rp12 c5 c2 c6 c18 c7 c8 c26 r18 r5 r20 r10 r13 r14 r15 r16 r8 r7 r6 r4 c27 r11 c28 r21 c29 r3 1.0 0.1 (0.039 0.004) 3.81 (0.150) max. 2.31 (0.091) ref. 4.19 (0.165) 1.80 (0.071) 3.98 (0.157) min. 47.40 (1.866) 11.40 (0.449) 31.75 (1.25) 3.98 0.1 (0.157 0.004) 20 (0.787) * for ddr333 consult factory
w3eg6464s-ad4 -bd4 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs march 2004 rev. 1 preliminary document title 512mb - 64mx64, ddr, sdram unbuffered w/pll revision history rev # history release date status rev 0 initial release 7-21-03 advanced rev 1 corrected incidentals (abreviations, symbols, etc.) 1.1 corrected pages 1-8 1.2 added ad4 and bd4 package options 1.3 added document title page 1.4 removed ed from part marking 3-4-04 preliminary
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